1. Field of the Invention
This invention relates to method and apparatus for verifying the validity of data stored in the volatile portion of the memory of a microprocessor, and more particularly to a method for extending the valid data time in the event of a power failure by verification of the integrity of volatile memory in a microprocessor of an electrical appliance.
2. Description of the Prior Art
With the increasing number of user programmable memory features in electrical appliances, such as time of day clocks, microwave ovens, dishwashers, and the like, it has become increasingly more important to survive momentary power interruptions to avoid the loss of user data supplied to the volatile memory of the microprocessor which controls the functions of the electrical appliance. This problem is found in all microprocessor/computer based systems, as well as, automotive accessories where there is a need to retain user enter data for as long as possible in the event of power interruption so that the system survives the interruption without the loss of user entered data. The loss of the user entered data requires that the user re-enter the data in the volatile memory.
In the appliance industry where the power source is an A.C. power line, it is usually required that the data stored in the volatile memory of the microprocessor by the user survive a power interruption of at least five seconds before the data has become corrupted. Studies have revealed that approximately 87% of all power interruptions are five seconds or less. This five second interval is known as the minimum "keep alive time" or the "data valid time". This time interval extends from the time when the main power source is interrupted to the point where user entered data in the volatile memory becomes invalid. The volatile memory can be corrupted by power interruption, power supply sagging, or power source transients.
It is the conventional practice to provide a five second minimum "data valid time" by large capacitors, batteries, or alterable nonvolatile memories (EEPROMS) which are expensive additions to digital controls. The conventional methods generally include very expensive material costs and require considerable engineering time to minimize material cost and obtain dependable results. Large electrolytic capacitors are the most common method for providing the minimum five second "data valid time".
Microcomputer manufacturers commonly define a threshold voltage below which the volatile memory is to be considered invalid. The volatile memory is commonly a CMOS static random access memory (RAM). Also in combination with large capacitors, it is known to detect a supply voltage level which places the microprocessor or microcomputer in a reset mode. This voltage level is well above the point at which the microcomputer manufacturer considers data in the volatile memory to become invalid but at any rate is accepted as the point at which data is invalid. This is done primarily to obtain a desired margin in design safety. When the main power source resumes the microcomputer is released from the reset mode and begins by initializing volatile memory, solely because the supply voltage has dropped below a predetermined level.
With the above known approach there is no regard for the actual state of the volatile memory. In many cases the memory is still valid, but is destroyed due to ignorance rather than the fact that the volatile memory is actually invalid.
While there have been proposed a number of methods for determining the point when data in the volatile memory becomes invalid, there is a need for a lower cost system with improved "data valid time". There is also a need that this method or apparatus to extend "data valid time" have improved tolerance of parameter variation so as to reduce system development costs. That is, to eliminate the need for testing and customization to each application. Previous methods have relied on measurement of a parameter such as power supply voltage and comparison to a fixed target which is an abstract and indirect approach. It is more flexible and efficient to determine data validity by integrating memory directly. Considering the fact that the volatile data memory remains valid to a much lower voltage level than conventionally specified by current microprocessor manufacturers. Therefore there is need to avoid the conventional practice of invalidating data beyond a certain supply voltage level well before the data in volatile memory actually becomes invalid. There is further need to extend the "data valid time" by verifying the memory in a microprocessor after a power outage rather than automatically assuming after a preselected period of time hat it is invalid.